What does #1 mean in verilog? [duplicate]

Question

I understand that always @(posedge clk) in verilog is a flip flop.

input ld;
reg ld_r;
always @(posedge clk) ld_r <= #1 ld;

What does #1 do in above code? I found it in verilog code for AES. I include a snippet of it below:

always @(posedge clk)
if(!rst)    dcnt <= #1 4'h0;
else
if(ld)      dcnt <= #1 4'hb;
else
if(|dcnt)   dcnt <= #1 dcnt - 4'h1;

always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;

Answer 1

Since you mention that always @(posedge clk) infers a flip-flop I assume you are interested in knowing what #1 is synthesized as in hardware. The answer is: nothing.

These delays will get ignored in synthesis, so if you use them in design code you run the risk of your simulation not matching your hardware.

Here is a paper that describes why you would want to add delays: http://sunburst-design.com/papers/CummingsSNUG2002Boston_NBAwithDelays.pdf