I'm having an unavoidable Quartus Syntax error

Question

Here is the code I have written:

reg number;
always @(posedge clk)
begin
case(SW[3:1])
        000: number = 32h'A65D;
        001: number = 32h'BAB9;
        010: number = 32h'9430;
        011: number = 32h'8BEB;
        100: number = 32h'7CB8;
        101: number = 32h'62F1;
        110: number = 32h'6EF9;
        111: number = 32h'5D5C;
        default: number = 32h'0000;
endcase
end

I keep getting an error in quartus for every line saying:

"Error (10170): Verilog HDL syntax error at test.v(181) near text "h"; expecting ";""

How I can resolve this error?

Answer 1

You need to specify a bit width for number; it is currently 1-bit wide and you likely want 32 bits. You need to add a size and a base radix (3'b) to each of the case items:

reg [31:0] number;
always @(posedge clk)
begin
case(SW[3:1])
        3'b000: number <= 32'hA65D;
        3'b001: number <= 32'hBAB9;
        3'b010: number <= 32'h9430;
        3'b011: number <= 32'h8BEB;
        3'b100: number <= 32'h7CB8;
        3'b101: number <= 32'h62F1;
        3'b110: number <= 32'h6EF9;
        3'b111: number <= 32'h5D5C;
        default: number <= 32'h0000;
endcase
end

You should use nonblocking assignments (<=) for sequential logic.

UPDATE: ...and of course after seeing Eugenio Lyatte's answer, fix the 'h syntax error, too.