Questions
Linux
Laravel
Mysql
Ubuntu
Git
Menu
HTML
CSS
JAVASCRIPT
SQL
PYTHON
PHP
BOOTSTRAP
JAVA
JQUERY
R
React
Kotlin
×
Linux
Laravel
Mysql
Ubuntu
Git
New posts in verilog
Shift Register Vs Multiplexer [closed]
May 10, 2026
hardware
vhdl
verilog
fpga
How to define and assign Verilog 2d Arrays
May 10, 2026
arrays
verilog
Parameterized number of cycle delays in verilog?
May 08, 2026
verilog
Generate custom waveform in verilog
May 08, 2026
verilog
Using parameters with for loop in verilog for bit selection
May 07, 2026
parameters
for-loop
verilog
hdl
VHDL equivalent to Verilog "10'h234"
May 05, 2026
vhdl
verilog
Verilog : Memory block Instantiation
May 03, 2026
verilog
fpga
register-transfer-level
RANDOM 0, 1, -1 IN VERILOG
May 02, 2026
verilog
fpga
hdl
how to generate a set of continuous one in verilog
Apr 30, 2026
verilog
How to simplify compound assignments in yosys
Apr 29, 2026
verilog
yosys
how to go about designing a 16 bit carry look ahead adder in verilog
Apr 23, 2026
verilog
Which way is better writing a register path in Verilog
Apr 20, 2026
verilog
What are best practices for optimizing pipeline throughput for fpga implementations?
Apr 21, 2026
vhdl
verilog
fpga
hdl
system-verilog
what is the best way to exchange 2 registers in Verilog
Apr 18, 2026
verilog
parameter based typedef in system Verilog
Apr 18, 2026
verilog
system-verilog
register-transfer-level
case statement with multiple cases doing same operation
Apr 16, 2026
verilog
system-verilog
How do I create a testbench for my Verilog code?
Apr 16, 2026
verilog
modelsim
How to check unknown logic in Verilog?
Apr 15, 2026
verilog
primes
system-verilog
What to do when a latch cannot be avoided?
Apr 15, 2026
hardware
verilog
fpga
xilinx
Older Entries »
Menu