Displaying the Verilog parameter name

Question

I am using the parameter keyword to define a state, i.e., RESET = 5'b00000. If I want to use $display to print out the state name instead of the binary representation, or display the state name in my simulation wave viewer, how can I do this? It doesn't work to try to print it out as a string (as you would expect), so I'm wondering if this can be done.

Answer 1

I do not know of a way to automatically $display the name of a parameter. However, if you don't mind duplicating your code, you could create a task (or function) to accomplish your goal:

    task show_name_state;
        case (state)
            5'b00000: $display("RESET");
            5'b00001: $display("WAIT");
        endcase
    endtask

    $display(state); show_name_state();

I know of at least one (expensive) Verilog debugger which has the capability to recognize parameters and automatically display their names in its waveform viewer: the Verdi (formerly Debussy) nWave tool can do this.

Answer 2

If your goal is just the display the name of the state during simulation, I will usually do something like

`ifdef SIMULATION
reg [127:0] __state__;
case (state)
  STATE_1 : __state__ = "STATE_1";
  STATE_2 : __state__ = "STATE_2";
  default : __state__ = "error";
endcase
`endif

Where state is the state register that has the parameter in question.