I was looking to add an error counter to a VHDL assert operation in existing code. Basically, I have code that looks like this:
assert data = good_data
report "Bad data"
severity error;
And I would like to add something like this to get triggered when the assertion occurs:
errors <= errors + 1;
Now I know I can achieve this by changing the assert to an if statement and then embedding the report statement and my error count increment withing the if statement. But I'm wondering if there is anyway to get more functionality out of the assert statement that is already there?
You could use the VUnit VHDL testing framework https://github.com/LarsAsplund/vunit which has check and check_equal procedures wrapping assert and counting the number of errors. The default behavior is to halt on first error such that it can be easily debugged.
I also believe the OSVVM AlertLogPkg.vhd has a similar feature. VUnit ships with OSVVM re-distributed so you could use it from there as well.
If you want to roll your own just make an procedure assert(cond : value; msg : string := "") that increments a shared counter variable in the same package.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With