Trying to blink LED in Verilog

Question

I have a CPLD with a 50Mhz clock.

This is my code:

module FirstProject(clk, LED);
  output LED;
  input  clk;

  reg [32:0] count1;
  reg        LEDstatus;


  assign LED = LEDstatus;

  always @ (posedge clk) begin
    if (count1 < 10000000) begin
      LEDstatus <= 0;
    end
    else begin
      LEDstatus <= 1;
    end
    count1 <= count1 +1;
  end

endmodule

I have no idea why this does not work. It deploys on CPLD, but light is always on

This code works on my cpld with the exact same pin assignments and timing constraints

http://www.fpga4fun.com/Opto2.html

Answer 1

The clock frequency is 50MHz, a On-Off loop is 2**33-1 (8589934591) cycles.

1/Hz = seconds
slowdown factor * 1/Hz = seconds to complete loop

This implies the LED is trying to flash at:

(8589934591 / 50000000) = 171s, slower than 1Hz

Anything over 25Hz would be not be perceived but that is not the issue here.

When the count is between 0 and 10000000 the light should be off:

10000000 / 50000000 = 0.2 Seconds

The off time is 0.2 seconds and the on time is about 170 seconds. It is likely that this ratio is very hard to observe. Switching to a 50/50 on/off ratio and a faster speed observation would be easier.

I would suggest making count1 24 bits wide and basing the output on the MSB of count1;

reg [23:0] count1; 

always @(posedge clk) begin
  LEDstatus <= count1[23];
  count1    <= count1 + 1;
end