Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in x86

Outputting integers in assembly on Linux

assembly x86 nasm

Why does Hyper-threading get reported as supported on processors without it?

x86 intel hyperthreading cpuid

How can I detect when Android x86 is emulating ARM?

android-ndk x86 arm

Automatically generate FMA instructions in MSVC

c++ visual-c++ x86 avx fma

How to ask GCC to completely unroll this loop (i.e., peel this loop)?

c gcc x86 hpc loop-unrolling

Can the LSD issue uOPs from the next iteration of the detected loop?

assembly x86 cpu-architecture intel-pmu

Utilizing the LDT (Local Descriptor Table)

c assembly x86

Why do I get a different SHA1 hash between Powershell and 32bit-Python on a system DLL?

python powershell x86 64-bit

Why is one of these sooooo much faster than the other?

c++ performance x86 inline-assembly

Is it legal to optimize away stores/construction of volatile stack variables?

c++ optimization x86 language-lawyer volatile

How to force NASM to encode [1 + rax*2] as disp32 + index*2 instead of disp8 + base + index?

assembly x86 nasm micro-optimization machine-code

Switch Case Assembly Language

assembly x86 switch-statement disassembly

Scope of MXCSR control register?

floating-point x86 sse cpu-registers fpu

_mm_set_epi8 - what does "set" mean?

x86 sse simd intel

SSE2 instruction to load integers in reverse order

x86 sse simd sse2

Intel x86 to ARM assembly conversion

c x86 arm intel-syntax

Generating a random number within range of 0-9 in x86 8086 Assembly

assembly random x86 x86-16

Skylake L2 cache enhanced by reducing associativity?

x86 cpu intel cpu-cache

Finding the most frequently occurring element in an SSE register

algorithm assembly x86 sse

What are the differences between the compress and expand instructions in AVX-512?

assembly x86 simd avx512
« Newer Entries Older Entries »