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New posts in x86
Stack Guard and Stack Smashing Protection - canaries, memory
Nov 09, 2017
gcc
random
linux-kernel
x86
protection
Is there any way to recompile binaries from x86 to ARM on linux?
Nov 17, 2022
linux
compilation
x86
arm
What code skeleton should I use for Intel 8086 DOS assembly?
Oct 22, 2021
assembly
x86
dos
x86-16
Is there any larger significance to this piece of translated assembly code?
Nov 06, 2022
c
algorithm
assembly
x86
reverse-engineering
Spinlock with XCHG unlocking
May 07, 2022
assembly
x86
synchronization
spinlock
Which Linux kernel function creates the 'process 0'?
Sep 20, 2022
c
assembly
linux-kernel
x86
boot
Portable efficient alternative to PDEP without using BMI2?
Nov 24, 2020
algorithm
assembly
x86
bit-manipulation
bmi
c# visual studio build exe with target anycpu but that determines its platform(x86/x64) on the calling process platform(x86/x64)
Dec 14, 2018
c#
visual-studio-2015
x86
target-platform
anycpu
Assembled c++ appears to contain superfluous instructions
Dec 30, 2020
c++
macos
assembly
optimization
x86
intel
Cache-friendly way to collect results from multiple threads
Apr 14, 2022
c++
multithreading
optimization
x86
cpu-cache
Using ymm registers as a "memory-like" storage location
Dec 07, 2020
assembly
x86
sse
avx
Intel's CLWB instruction invalidating cache lines
Apr 17, 2022
x86
intel
cpu-architecture
cpu-cache
persistent-memory
How do I store the value of a register into a memory location pointed to by a pointer?
Oct 15, 2017
c++
pointers
assembly
x86
Recreate dead threads after a fork
Oct 03, 2021
c
linux
64-bit
x86
fork
Performance difference between system call vs function call
Oct 24, 2022
performance
x86
kernel
system-calls
Atomic Minimum on x86 using OpenMP
Jul 11, 2019
c++
x86
openmp
atomic
minimum
Can a shift using the CL register result in a partial register stall?
Oct 15, 2017
performance
assembly
x86
bit-shift
Why is protected mode needed in addition to compatibility mode in Intel x86 64 bit CPUs?
Oct 22, 2022
x86
cpu
x86-64
protected-mode
How to merge a scalar into a vector without the compiler wasting an instruction zeroing upper elements? Design limitation in Intel's intrinsics?
Dec 26, 2019
c
gcc
x86
sse
intrinsics
Best way to load/store from/to general purpose registers to/from xmm/ymm register
Nov 03, 2022
assembly
x86
simd
sse2
avx2
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