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New posts in x86

How many clock cycles does cost AVX/SSE exponentiation on modern x86_64 CPU?

c++ x86 x86-64 sse avx

What does mov bl do in assembly

c++ assembly x86

difference between load1 and broadcast intrinsics

x86 sse simd intrinsics intel

why do repe and repne do the same before movsb?

assembly x86 repeat machine-code instructions

8086 assembly on DOSBox: Bug with idiv instruction?

assembly x86 x86-16 tasm dosbox

When to use ADOX instead of ADCX?

assembly x86 adx

x86 register flag abbreviations

assembly x86 masm eflags

How can I find out which cache line is touched by an instruction on an Intel processor?

caching x86

x86 XOR opcode differences

assembly x86 bit-manipulation opcode instruction-encoding

Do prefetch instructions need to return their result before they retire?

performance x86 prefetch

The inner workings of Spectre (v2)

x86 intel cpu-architecture branch-prediction spectre

Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?

assembly x86 intel cpu-architecture instruction-set

x86 Assembly Why use Push/Pop instead of Mov?

assembly x86 exploit shellcode

GCC wrongly optimizes a pointer-equality test for a variable at a custom address

c gcc optimization x86 x86-64

Are the Linux/SMP spinlocks unnecessarily slow?

x86 linux-kernel spinlock

Intel 64 and IA-32 | Atomic operations including acquire / release semantic

assembly locking x86 intel memory-fences

On x86 if [mem] is not 32-bit aligned, can "lock inc [mem]" still work fine?

multithreading assembly x86 multiprocessing

jmp FWORD PTR [eax-0x67]?

assembly x86

x86 Assembly Force Cache Store

c caching assembly x86

Assembly language using shl to multiply by an odd number?

assembly x86
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