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New posts in x86

where goes the ret instruction of the main

c assembly x86 return

Generating a 64-byte read PCIe TLP from an x86 CPU

x86 pci-e

ASM: operand type mismatch for `cmp'

assembly x86

Does clflush also remove TLB entries?

performance caching x86 cpu-cache

Is mov + mfence safe on NUMA?

c++ x86 memory-model numa stdatomic

Why use .data instead of reserving space in .bss and initializing at runtime, for variables in assembly/C?

c linux assembly memory x86

AVX2 Transpose of a matrix represented by 8x __m256i registers

c x86 transpose simd avx2

Cache coherence literature generally only refers store buffers but not read buffers. Yet one somehow needs both?

concurrency x86 cpu-architecture memory-model

Why _umul128 works slower than scalar code for mul128x64x2 function?

c++ x86 simd avx micro-optimization

How is the transitivity/cumulativity property of memory barriers implemented micro-architecturally?

x86 x86-64 cpu-architecture memory-barriers micro-architecture

Why are there too many demand rfo offcore responses /offcore requests?

assembly x86 x86-64 cpu-cache rfo

Can a “PUSH” instruction's operation be performed using other instructions?

assembly x86 nasm stack-memory instruction-set

Does RDTSCP increment monotonically across multi-cores?

c++ assembly x86 multicore rdtsc

What is the fastest virtual machine design for x86?

assembly x86 vm-implementation

Why do segments begin on paragraph boundaries?

memory-management assembly x86

CPUID: Why must MISC_ENABLE.LCMV be set to 0 for some functions? Can I temporarily overwrite it?

assembly x86 x86-64 cpuid msr

Loading a file on an ISO 9660 File System

assembly filesystems x86 bios iso9660

Stack allocation, why the extra space?

gcc assembly x86 stack memory-alignment

How does this asm code setup SEH?

exception assembly x86 masm seh

Least intrusive compile barrier for Java on x86

java performance memory x86 barrier
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