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New posts in x86

What's the relative speed of floating point add vs. floating point multiply

floating-point x86 mips numerical-computing flops

x86 Assembly pushl/popl don't work with "Error: suffix or operands invalid"

assembly x86 x86-64

What's the purpose of the rotate instructions (ROL, RCL on x86)?

assembly x86 cpu-architecture bit-shift instruction-set

What are CLD and STD for in x86 assembly language? What does DF do?

assembly x86

Differences Between ARM Assembly and x86 Assembly [closed]

assembly embedded x86 arm

Crash with icc: can the compiler invent writes where none existed in the abstract machine?

c++ x86 language-lawyer simd icc intel

Physical or virtual addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3?

caching x86 virtual-memory tlb virtual-address-space

How expensive is it to convert between int and double?

c++ x86 c++-cli x86-64 micro-optimization

What do the E and R prefixes stand for in the names of Intel 32-bit and 64-bit registers?

assembly x86 64-bit x86-64 cpu-registers

What x86 register denotes source location in movsb instruction?

assembly x86 cpu-registers

What is the size of float and double in C and C++? [duplicate]

c++ c floating-point x86 64-bit

How to check if compiled code uses SSE and AVX instructions?

c++ assembly x86 g++ simd

Cycles/cost for L1 Cache hit vs. Register on x86?

performance x86 cpu-architecture cpu-cache micro-optimization

Intel x86 vs x64 system call

linux assembly x86 x86-64 interrupt

Is performance reduced when executing loops whose uop count is not a multiple of processor width?

performance assembly x86 cpu-architecture micro-optimization

x86 assembly abs() implementation?

assembly x86

In what situation would the AVX2 gather instructions be faster than individually loading the data?

assembly optimization x86 vectorization avx2

Why do virtual memory addresses for linux binaries start at 0x8048000?

linux x86 elf memory-layout intel

Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC

performance x86 x86-64 cpu-architecture rdtsc

Atomicity on x86

c++ multithreading x86 atomic memory-barriers
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