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New posts in x86

Intel CPUs Instruction Queue provides static branch prediction?

performance assembly x86 cpu-architecture branch-prediction

Addressing Modes in Assembly Language (IA-32 NASM)

assembly x86 nasm addressing-mode

How to power down the computer from a freestanding environment?

c assembly operating-system x86 system-shutdown

How to use a logical address with an FS or GS base in gdb?

gdb x86 memory-segmentation

Floating Point Program gives Invalid Result

assembly floating-point x86 masm irvine32

Difference between dts and ACPI

linux x86 linux-device-driver device-tree acpi intel

x86 assembly programming loops with ecx and loop instruction versus jmp + j<condition>

loops assembly x86

What's the point of the VPERMILPS instruction (_mm_permute_ps)?

assembly x86 avx instruction-set

mov eax, large fs:30h

debugging assembly x86 ida mov

SIMD instructions for floating point equality comparison (with NaN == NaN)

assembly floating-point x86 x86-64 simd intel

Intel Intrinsics guide - Latency and Throughput

performance x86 intel sse intrinsics

Sum reduction of unsigned bytes without overflow, using SSE2 on Intel

x86 sse simd sse2 sse3

Can the Intel performance monitor counters be used to measure memory bandwidth?

performance x86 intel-pmu memory-bandwidth

Parallel memory access on modern processors

memory parallel-processing x86 multicore bus

Does [ebp*2] reference DS or SS segment?

assembly x86 nasm instructions opcode

Using __m256d registers

c++ x86 intel simd avx

Load address calculation when using AVX2 gather instructions

x86 sse simd avx2

Why is movl preferred to movb when translating a C downcast from unsigned int to unsigned char?

c assembly gcc x86 micro-optimization

SIMD the following code

c x86 sse simd

Linux asm("int $0x0") vs division by zero

c linux assembly x86
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