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New posts in x86-64

Why doesn't the same generated assembler code lead to the same output?

intel c floating-point x86-64 floating-accuracy icc

Self-modifying code sees a 0xCC byte but the debugger doesn't show it?

assembly gdb x86-64 breakpoints self-modifying intel

How to execute a call instruction with a 64-bit absolute address?

assembly x86-64 nasm jit function-call

Was there a P4 model with double-pumped 64-bit operations?

x86 x86-64 intel cpu-architecture

Can rip be used with another register with RIP-relative addressing?

assembly x86-64 addressing-mode

UEFI boot services CreateEvent() returning status EFI_INVALID_PARAMETER

assembly x86 x86-64 nasm uefi

How to prevent gcc optimization breaking rep movsb code? [duplicate]

c gcc optimization x86-64 inline-assembly

How to compile assembly whose entry point is not main with gcc?

gcc assembly x86-64

Storing individual doubles from a packed double vector using Intel AVX

x86 x86-64 sse avx

Choose the 32 or 64 bit version of an app from command line

macos architecture command-line x86-64 i386

Using RIP-relative addressing in OSX x64 assembly

macos assembly 64-bit nasm x86-64

Why does CR3 register contents vary, when read each time from a kernel module?

linux linux-kernel x86 linux-device-driver x86-64

Why does the Solaris assembler generate different machine code than the GNU assembler here?

linux assembly solaris x86-64

Counting number of instructions executed by a binary using pin, perf and valgrind

c assembly valgrind x86-64 perf

With Hyper Threading, threads of one physical core are exchanging via what level of cache L1/L2/L3?

multithreading x86 x86-64 smt hyperthreading

X86_64 - assembly - Why displacement not 64 bits?

assembly x86-64 memory-address

How can gcc/clang assume a string constant's address is 32-bit?

c linux linker x86-64 elf

Why does the compiler allocate more than needed in the stack?

c gcc stack x86-64 allocation

g++ Optimization Flags: -fuse-linker-plugin vs -fwhole-program

intel c++ linux g++ x86-64 ld

Do all 64 bit intel architectures support SSSE3/SSE4.1/SSE4.2 instructions?

intel x86-64 cpu-architecture simd
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