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New posts in verilog
Is there a way to define something like a C struct in Verilog
Oct 02, 2022
struct
verilog
hdl
Verify Parameters in Verilog
Sep 29, 2022
verilog
hdl
xilinx-ise
Simple Verilog VPI module to open audio files
Apr 21, 2022
audio
signal-processing
verilog
libsndfile
icarus
Alternatives to $readmemh in Verilog
Jan 11, 2021
verilog
Accessing inputs and outputs in sub-modules from testbench
May 13, 2022
verilog
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Verilog register cannot be driven by primitives or continuous assignment
Oct 29, 2021
verilog
Is there a way to do nested generate statements in Verilog?
Dec 06, 2018
verilog
Why use functions in verilog when there is module
Oct 23, 2022
verilog
hdl
hardware-programming
How to make the 2-complement of a number without using adder
Nov 10, 2022
vhdl
verilog
fpga
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always block @posedge clock
Sep 12, 2022
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Piggybacking to UVM error
Jun 18, 2022
verilog
system-verilog
uvm
Icarus verilog dump memory array ($dumpvars)
Oct 25, 2022
arrays
memory
verilog
dump
icarus
Mixing blocking and non-blocking assign in Verilog (or not!)
May 07, 2022
verilog
Connecting a module output to a register
Sep 25, 2022
verilog
How to generate delay in verilog for synthesis?
Apr 01, 2022
verilog
Is there a way to get the name a Verilog module was instantiated with?
Nov 06, 2022
verilog
Syntax for using an array of wires as input
Nov 06, 2019
arrays
verilog
Verilog to GDSII compiler (open-source)
Jan 07, 2022
compiler-construction
verilog
circuit
vlsi
VIM highlight matching begin/end
Oct 21, 2022
vim
syntax
syntax-highlighting
verilog
vim-syntax-highlighting
Generic in verilog from a vhdl programmer
Jun 23, 2022
syntax
vhdl
verilog
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