Questions
Linux
Laravel
Mysql
Ubuntu
Git
Menu
HTML
CSS
JAVASCRIPT
SQL
PYTHON
PHP
BOOTSTRAP
JAVA
JQUERY
R
React
Kotlin
×
Linux
Laravel
Mysql
Ubuntu
Git
New posts in simd
Is there a C implementation for GNU ARM NEON intrinsics? [closed]
Aug 05, 2022
c
gcc
arm
simd
neon
access violation _mm_store_si128 SSE Intrinsics
Feb 28, 2019
intel
c++
x86
simd
sse
intrinsics
SSE2 optimization for converting from RGB565 to RGB888 (no alpha channel)
Mar 24, 2022
c++
simd
intrinsics
sse2
color-conversion
Is vec_sld endian sensitive?
Nov 12, 2022
c
endianness
simd
powerpc
altivec
simd_mul vs * operator
Feb 28, 2020
swift
xcode
simd
improve locality and decrease Cache pollution in a medical image reconstruction implementation
Jun 17, 2022
c
caching
optimization
blocking
simd
SSE2 instruction to typecast an integer register to short register and vice-versa
Jul 14, 2022
x86
sse
simd
sse2
Setting last or first n bits in SSE register
Nov 15, 2021
c++
x86
sse
simd
intrinsics
Compress mask using AVX intrinsics
Jul 18, 2021
c
x86
simd
intrinsics
avx
C++ Centralizing SIMD usage
Aug 28, 2022
c++
optimization
simd
OpenMP 4 aligned option?
Jul 16, 2022
c++
c
openmp
simd
AVX segmentation fault on linux [closed]
Oct 18, 2022
c++
linux
g++
simd
avx
Using values from `__m256i` to access an array efficiently - SIMD [closed]
May 26, 2022
c++
arrays
simd
avx2
Resize 8-bit image by 2 with ARM NEON
May 11, 2022
image
image-processing
arm
simd
neon
Using fast Intel random generator(SSE2) fails with stack around ... is corrupted
Jan 29, 2021
c++
random
sse
simd
How to access SIMD vector elements when overloading array access operators?
Aug 22, 2021
c++
operator-overloading
clang
simd
avx
Intel SIMD - How can I check if an __m256* contains any non-zero values
Jul 11, 2018
c++
simd
intrinsics
avx
Floating-point number vs fixed-point number: speed on Intel I5 CPU
Oct 02, 2019
performance
matrix
sse
simd
openblas
What is the difference between loadu_ps and set_ps when using unformatted data?
Nov 24, 2021
sse
simd
intrinsics
sse2
Do all 64 bit intel architectures support SSSE3/SSE4.1/SSE4.2 instructions?
Sep 09, 2022
intel
x86-64
cpu-architecture
simd
« Newer Entries
Older Entries »