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New posts in memory-model

Concurrency and memory models

C11/C++11 weak memory benchmarks

Is the transformation of fetch_add(0, memory_order_relaxed/release) to mfence + mov legal?

Does atomic_thread_fence(memory_order_seq_cst) have the semantics of a full memory barrier?

Example for a correctly synchronized program with data races in Java memory model

java memory-model jls

How causal consistency is different to sequential consistency?

C++ How is release-and-acquire achieved on x86 only using MOV?

Does the MOV x86 instruction implement a C++11 memory_order_release atomic store?

Will two atomic writes to different locations in different threads always be seen in the same order by other threads?

C11 Atomic Acquire/Release and x86_64 lack of load/store coherence?

Are synchronizes-with edegs compiler re-ordering barriers in both directions?

Confusion about implementation error within shared_ptr destructor

Using an atomic read-modify-write operation in a release sequence

Reading shared variables with relaxed ordering: is it possible in theory? Is it possible in C++?

Can std::atomic memory barriers be used to transfer non-atomic data between threads?

Implementing an acquire for a release from Unsafe.putOrdered*()?

C11/C++11 Memory Model

c++ gcc c++11 memory-model c11

What's are practical example where acquire release memory order differs from sequential consistency?

How to understand RELAXED ORDERING in std::memory_order (C++)

c++ atomic memory-model

In C/C++, are volatile variables guaranteed to have eventually consistent semantics betwen threads?