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New posts in cpu-cache
Does prefetching a write ever affect single core performance?
Oct 09, 2022
x86-64
multicore
cpu-architecture
prefetch
cpu-cache
Typical L1 and L2 access latency for SoCs made of ARM Cortex-A9
Oct 07, 2022
arm
cpu-cache
tegra
omap
Usage of PLD instruction
Sep 23, 2021
arm
cpu-cache
mmu
cortex-a8
struct of arrays and memory access patterns
Jul 17, 2022
c
arrays
struct
simd
cpu-cache
Is memory outside each core always conceptually flat/uniform/synchronous in a multiprocessor system?
Jun 01, 2022
memory
cpu-architecture
cpu-registers
cpu-cache
memory-barriers
Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
Jun 06, 2022
intel
assembly
x86
cpu-cache
micro-optimization
compare-and-swap
What does the processor do while waiting for a main memory fetch
Jun 04, 2016
cpu
cpu-architecture
cpu-cache
What is reference when it says L1 Cache Reference or Main Memory Reference
Sep 13, 2022
performance
latency
cpu-cache
system-design
Do store instructions block subsequent instructions on a cache miss?
Nov 09, 2022
c++
concurrency
x86
cpu-architecture
cpu-cache
When accessing memory, will the page table accessed/dirty bit be set under a cache hit situation?
Nov 17, 2022
cpu-architecture
cpu-cache
mmu
page-tables
CPU cache: does the distance between two address needs to be smaller than 8 bytes to have cache advantage?
Nov 05, 2022
caching
cpu-architecture
cpu-cache
Why doesn't RFO after retirement break memory ordering?
Jul 15, 2022
assembly
x86-64
cpu-architecture
cpu-cache
rfo
How to find number of conflict misses in a cache simulator
Aug 23, 2022
caching
memory
cpu-architecture
computer-architecture
cpu-cache
Inclusive or exclusive ? L1, L2 cache in Intel Core IvyBridge processor
Sep 08, 2022
c
cpu-architecture
processor
cpu-cache
Can a lower level cache have higher associativity and still hold inclusion?
Sep 07, 2022
caching
memory
memory-management
cpu-architecture
cpu-cache
Array of Structures (AoS) vs Structure of Arrays (SoA) on random reads for vectorization
Nov 17, 2022
c++
parallel-processing
vectorization
cpu-cache
Efficient memory bandwidth use for streaming
Aug 18, 2022
optimization
streaming
cpu-cache
memory-bandwidth
What happens with a non-temporal store if the data is already in cache?
Jul 16, 2022
c++
x86
sse
cpu-cache
What is PDE cache?
Sep 04, 2019
arm
computer-architecture
tlb
cpu-cache
mmu
The ordering of L1 cache controller to process memory requests from CPU
Jun 20, 2022
x86
hardware
cpu-architecture
cpu-cache
memory-barriers
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