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New posts in cpu-architecture
Understanding Amdahl's law
Oct 31, 2025
performance
parallel-processing
cpu-architecture
ARM Cortex-M7 assembly timing on simple delay loop - how to explain results?
Oct 31, 2025
assembly
arm
cpu-architecture
cortex-m
superscalar
Why the number of x86 int registers is 8?
Oct 31, 2025
assembly
x86
x86-64
cpu-architecture
cpu-registers
Why is my loop much faster when it is contained in one cache line?
Oct 30, 2025
performance
caching
x86
cpu-architecture
amd-processor
Does Intel Cache Allocation Technology allow hits from CPUs in one group on cache lines in another group?
Oct 30, 2025
cpu
cpu-architecture
intel
cpu-cache
How does CPU access BIOS instructions stored in external memory?
Oct 30, 2025
cpu-architecture
bios
firmware
How does a 6502 CPU have an 8-bit data bus?
Oct 30, 2025
cpu
cpu-architecture
6502
How does kernel know physical memory base address?
Oct 28, 2025
linux
linux-kernel
kernel
cpu-architecture
ram
Flynn's Bottleneck - maximum speedup 2
Oct 28, 2025
cpu-architecture
Bottleneck when using indexed addressing modes
Oct 27, 2025
x86-64
intel
cpu-architecture
micro-optimization
addressing-mode
What is the difference between pipeline and lane in terms of CPU architecture?
Oct 29, 2025
gpu
cpu-architecture
simd
Is uops.info wrong about vinserti128?
Oct 28, 2025
assembly
x86
cpu-architecture
simd
avx2
Which type of assembler jump instruction is most useful?
Oct 26, 2025
assembly
cpu-architecture
low-level
Temporality of ST64B and MOVDIR64B
Oct 28, 2025
assembly
x86-64
cpu-architecture
arm64
micro-architecture
Why is my benchmark using __mm_prefetch slower?
Oct 27, 2025
c++
x86
cpu-architecture
prefetch
How can Intel and AMD be different but still compatible?
Oct 27, 2025
optimization
x86
intel
cpu-architecture
amd-processor
Would an Instruction Set Architecture benefit from both an ADC and SBC, or could all carry instructions repeat the previous type?
Oct 25, 2025
assembly
cpu-architecture
instruction-set
carryflag
Why is program counter incremented by 1 if memory organised as word and by 2 in case of bytes?
Oct 25, 2025
assembly
memory
cpu-architecture
Why unlamination of μops necessary?
Oct 26, 2025
x86
cpu
intel
cpu-architecture
Reading Current Uncore Frequency and Setting Uncore Frequency Multipliers
Oct 24, 2025
x86
intel
cpu-architecture
msr
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