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New posts in computer-architecture

Does a hyperthreading CPU implement parallelism or just concurrency?

Writing a Register File in VHDL

Octal full adder How to

Why do we need different CPU architecture for server & mini/mainframe & mixed-core? [closed]

MIPS and ARM differences

"data bit" capacity vs "overhead bit" size?

MIPS Pipeline Forwarding (double data hazard)

Determine the critical path in the data flow

Deploying to OS X 10.6 and "-fobj-arc is not supported on platforms using the legacy runtime"

Android CPU register names?

How cache memory works?

Is memory latency affected by CPU frequency? Is it a result of memory power management by the memory controller?

Write a program to get CPU cache sizes and levels

SIMD vs Vector architectures

How do computers translate everything to binary? When they see a binary code, how do they know if it represents a number or a word or an instruction?

Why are GPIOs used?

Calculating average memory access time in a system implementing cache memory

What is "false sharing"? How to reproduce / avoid it?

word size and data bus

computer-architecture

How much time does it take to fetch one word from memory?