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New posts in assembly

Why does x86 nopl instruction take an operand? [duplicate]

assembly x86 x86-64 instructions nop

Meaning of BND RET in x86

assembly x86 return disassembly opcode

Efficiently find least significant set bit in a large array?

c assembly bit-manipulation x86-64 avx

clang (LLVM) inline assembly - multiple constraints with useless spills / reloads

gcc assembly clang x86-64 inline-assembly intel

Instruction Level Profiling: The Meaning of the Instruction Pointer?

performance assembly profiling x86-64 low-level

Stable raster on C64

assembly 6510

Optimizing a bit-manipulating algorithm in GameBoy Z80

assembly bit-manipulation z80 gameboy

Is there a complete x86 assembly language reference that uses AT&T syntax? [closed]

assembly x86 intel

Fast signed 16-bit divide by 7 for 6502

assembly division micro-optimization integer-division 6502

Is there a penalty when base+offset is in a different page than the base?

performance assembly x86 micro-optimization

MIPS load word syntax

assembly mips

Inline assembly in Haskell

haskell compiler-construction assembly inline-assembly ghc

MIPS assembly for a simple for loop

loops assembly mips mips32

ARM: Why do I need to push/pop two registers at function calls?

assembly arm cpu-registers stack-memory abi

How is floating point conversion actually done in C++?(double to float or float to double)

c++ assembly floating-point type-conversion

What are the .w and .n suffixes added to arm assembly instructions?

assembly arm

What considerations go into predicting latency for operations on modern superscalar processors and how can I calculate them by hand?

assembly x86-64 pipeline latency superscalar

Why are RISC-V S-B and U-J instruction types encoded in this way?

assembly encoding riscv machine-code instruction-set

What CPU registers are to be restored at the end of an asm procedure in Delphi

delphi assembly cpu-registers basm

Why are Intel x87 registers 80 bits wide?

assembly x86 intel cpu-architecture x87
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