What does `&` operator do to a standard logic vector?

Question

I'm looking at some code that does the following:

signal1 : std_logic
vector1 : std_logic_vector

vector1 <= vector1(20 downto 1) & signal1;

I assume that a vector1(20 downto 1) produces the following:

[20 19 18 ... 3 2 1]

but what I don't understand is what the & does to it. Does it return a 0 if signal1 is 0 and the vector created if signal1 is 1?

Answer 1

& is not comparison : it's the concatenation operator. It builds a larger array (vector, string) out of smaller ones or components (bits, characters).

vector1(20 downto 1) simply takes a 20 bit slice from vector1 : & appends signal1 to it, making a new 21 bit vector. This is then assigned by <= to vector1, which I assume must be 21 bits long (or you have a compile time error!)

If vector1 is declared as

signal vector1 : std_logic_vector(21 downto 1);

then this is a shift register; every such operation is a left shift by 1 bit, with a new LSB from signal1.