What ${CC} means in makefile?

Question

I have makefile that uses ${CC} variable for compiler selection:

${CC} $(CFLAGS) aaa.cpp -o aaa.o

During make ${CC} brings cc compiler. But there is no definition of ${CC} in whole makefile. How this variable gets cc?

Answer 1

Some of the variables make uses in its implicit rules like CC have default values.

You can read more about them in the GNU make documentation about variables used in implicit rules:

In general variables can also get their value through the environment or by passing command line arguments to make, as well as other ways for some special variables as documented here.