VHDL what is more efficient to use : an integer with range or a std_logic_vector

Question

If i declare a signal integer range 0 to 6 , will it be better or worse opposing to declaring a std_logic_vector (2 downto 0) to do the exact same job.I am referring to design cost so that i can decide whether to use an integer with a small range or a one-hot representation with a vector.

To put it plainly how much space will be reserved for an integer range 0 to n ?

Answer 1

If a synthesis tool implements an integer with range 0 to N with minimum resources, it will have a size of:

integer range 0 to N : std_logic_vector(ceil(log2(N + 1)) - 1 downto 0)

So your integer range 0 to 6 will have the size of a std_logic_vector(2 downto 0).

But the VHDL language itself does not have a cost function for different data structures, since the cost depends on the implementation. Simulation tools implement the data structures one way, and synthesis tools does it differently.

For example, the size in a FPGA depends on how good a job the synthesis tool does. The synthesis tool must make an implementation where the operation of the resulting design is equivalent to the VHDL specification, but the synthesis tool is free to make an implementation that is larger than required, for example by implementing all integers 32-bit std_logic_vector.

The best way to find out the actually size is to make small experiments with the synthesis tools, whereby you will also learn a lot about synthesis tools and VHDL implementations.