SystemVerilog interface - Passing parameters after module declaration

Question

Given the following module declaration:

module ( myinterface.mymodport mybus, ... );

And assuming that myinterface has parameters, how do I specify them?

The interface instantiation happens only in the testbench, but now I want to synthesize the DUT, so the TB disappears.

Answer 1

This is an oversight in the SystemVerilog LRM. There's no syntax to specify a required set of parameters for an interface in a module header.

You might check your synthesis tool to see if they provide any way of specifying parameter overrides for the top-level synthesis instance.