System Verilog: enum inside interface

Question

I have an interface:

interface my_intf();
typedef enum logic [1:0] {
   VAL_0 = 2'b00,
   VAL_1 = 2'b01,
   VAL_2 = 2'b10,
   VAL_3 = 2'b11
} T_VAL;
T_VAL val;
endinterface

My module uses this interface:

my_intf intf;

The problem is to assign the val with a value from the enum.

I can assign it as:

intf.val = 0; (and receiving warning or error)

but not as:

intf.val=VAL_0;

Nor as

intf.val = my_intf.T_VAL.VAL_0

How I overcome that problem?

Answer 1

I have only dealt with packages for containing enums before, and avoid interfaces. This is how I use packages. Import the package before the module definition with which you want to use it:

import my_intf_pkg::* ;

module bla(
  output my_val_t intf
);

  initial begin
    intf = VAL_0 ;
  end

endmodule

The package containing enums might look like:

package my_intf_pkg;
  typedef enum logic [1:0] {
     VAL_0 = 2'b00,
     VAL_1 = 2'b01,
     VAL_2 = 2'b10,
     VAL_3 = 2'b11
  } my_val_t;
endpackage : my_intf_pkg

Note that the VAL_0 etc are global and not tied to the T_VAL typedef. Therefore I often make them a bit more unique including the typedef in the name. T_VAL_0 for T_VAL typedefs etc.

Here is an example on EDAplayground.