std_logic_vector to integer conversion vhdl

Question

I faced with conversion problem/I read a lot of similar topics but my code still not working.Could you pls give me some hints. Quartus give me error:

Error (10476): VHDL error at true_dual_port_ram_single_clock.vhd(44): type of identifier "random_num_i" does not agree with its usage as "std_logic_vector" type

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity write_ram is
  generic(width : integer := 32);
  port(clock_i  : IN  STD_LOGIC;
       we_w     : IN  STD_LOGIC;
       wr_addr  : IN  INTEGER RANGE 0 to 31;
       read_add : IN  INTEGER RANGE 0 to 31;
       q_out    : out STD_LOGIC_VECTOR(2 DOWNTO 0)
  );
end write_ram;

architecture rtl of write_ram is
  --- Component decalarartion
  component random is
    port(clk        : in  std_logic;
         random_num : out std_logic_vector(width - 1 downto 0) --output vector 
    );
  end component;

  component single_clock_ram is
    port(clock         : IN  STD_LOGIC;
         data          : IN  INTEGER RANGE 0 to 31;
         write_address : IN  INTEGER RANGE 0 to 31;
         read_address  : IN  INTEGER RANGE 0 to 31;
         we            : IN  STD_LOGIC;
         q             : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
    );
  end component;
  for all : random use entity work.random(rtl);
  for all : single_clock_ram use entity work.single_clock_ram(rtl);
  Signal random_num_i : INTEGER RANGE 0 to 31; --interanal signals
begin
  -- Component Instantiation

  C1 : random Port map(
      clk        => clock_i,
      --random_num <=to_integer(to_signed(random_num_i))
      random_num => random_num_i
    );
  random_num <= to_integer(to_signed(random_num_i)); -- error

  C2 : single_clock_ram
    Port map(
      clock         => clock_i,
      we            => we_w,
      read_address  => read_add,
      write_address => wr_addr,
      data          => random_num_i,
      q             => q_out
    );

end rtl;

Answer 1

Your question isn't an MCVE with the configuration specifications for random and single_clock_ram present. You didn't supply the entity declarations and architecture bodies (rtl) for them.

With them commented out this analyzes:

library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_signed.all;  -- NOT USED
-- use ieee.std_logic_unsigned.all;  -- NOT USED
use ieee.numeric_std.all;
-- use ieee.std_logic_arith.all;  -- NOT USED

entity write_ram is
  generic (width:  integer := 32);
  port (clock_i:   in  std_logic;
        we_w:      in  std_logic;
        wr_addr:   in  integer range 0 to 31;
        read_add:  in  integer range 0 to 31;
        q_out:     out std_logic_vector(2 downto 0)
  );
end entity write_ram;

architecture rtl of write_ram is
  --- component declaration
  component random is
    port (clk:         in  std_logic;
         random_num:   out std_logic_vector(width - 1 downto 0) --output vector 
    );
  end component;

  component single_clock_ram is
    port (clock:          in  std_logic;
          data:           in  integer range 0 to 31;
          write_address:  in  integer range 0 to 31;
          read_address:   in  integer range 0 to 31;
          we:             in  std_logic;
          q:              out std_logic_vector(2 downto 0)
    );
  end component;
  -- for all:  random use entity work.random(rtl);
  -- for all:  single_clock_ram use entity work.single_clock_ram(rtl);
  signal random_num_i:  integer range 0 to 31; -- internal signals 
  signal random_num:   std_logic_vector(width - 1 downto 0); -- added
begin
  -- component instantiation

  c1:  random port map (
      clk        => clock_i,
      -- random_num <=to_integer(to_signed(random_num_i))
      -- random_num => random_num_i  -- DELETED
      random_num => random_num   -- ADDED
    );
  -- random_num <= to_integer(to_signed(random_num_i)); -- error DELETED
  random_num_i <= to_integer(signed(random_num));   -- ADDED

  c2:  single_clock_ram
    port map (
      clock         => clock_i,
      we            => we_w,
      read_address  => read_add,
      write_address => wr_addr,
      data          => random_num_i,
      q             => q_out
    );

end architecture rtl;

Note there's been a random_num std_logic_vector declared to hook up to the output of random, which is converted an integer random_num_i used as an input to single_clock_ram data. The output q from the single_clock_ram looks a bit suspicious, should that be an integer or a wider std_logic_vector?