SPI with NXP CLRC663 : read only 0xFF

Question

I am currently working on an SPI communication between an NXP LPC55S06 processor (from the LPC55S06-EVK demoboard) and an NXP CLRC663.

I integrated the NXP NFC library to initialize the CLRC663 and configured the SPI pinouts in the .mex file. I have done my wiring and can verify the sending of SPI commands:

My problem is that the CLRC663 never responds to the commands I send it.

I have already checked my wiring several times and I think the problem is software. Since the problem can neither come from the NFC lib nor from the FSL drivers specific to the LPC55S06 processor, I suspect that it would come from the SPI configuration done by this code (called by the NFC lib):

#include "phDriver.h"
#include <board.h>
#include "BoardSelection.h"
#include "fsl_spi.h"
#define PHBAL_REG_LPCOPEN_SPI_ID               0x0DU       /**< ID for LPC Open SPI BAL component */


/**
* \brief Initialize the LPC Open SPI BAL layer.
*
* \return Status code
* \retval #PH_DRIVER_SUCCESS Operation successful.
* \retval #PH_ERR_INVALID_DATA_PARAMS Parameter structure size is invalid.
*/
phStatus_t phbalReg_Init(
                                      void * pDataParams,
                                      uint16_t wSizeOfDataParams
                                      )
{
    spi_master_config_t masterConfig = {0};
    if((pDataParams == NULL) || (sizeof(phbalReg_Type_t) != wSizeOfDataParams))
    {
        return (PH_DRIVER_ERROR | PH_COMP_DRIVER);
    }

    ((phbalReg_Type_t *)pDataParams)->wId      = PH_COMP_DRIVER | PHBAL_REG_LPCOPEN_SPI_ID;
    ((phbalReg_Type_t *)pDataParams)->bBalType = PHBAL_REG_TYPE_SPI;

    /* reset FLEXCOMM for SPI */
    RESET_PeripheralReset(LPC_SPI_NFC_RST);

    SPI_MasterGetDefaultConfig(&masterConfig);
    masterConfig.baudRate_Bps=7000000u; //7MHz
    SPI_MasterInit(LPC_SPI_NFC, &masterConfig,  LPC_SPI_NFC_CLOCKRATE);
    NVIC_SetPriority(LPC_SPI_NFC_IRQ,  7U);

    return PH_DRIVER_SUCCESS;
}

phStatus_t phbalReg_Exchange(
                                        void * pDataParams,
                                        uint16_t wOption,
                                        uint8_t * pTxBuffer,
                                        uint16_t wTxLength,
                                        uint16_t wRxBufSize,
                                        uint8_t * pRxBuffer,
                                        uint16_t * pRxLength
                                        )
{
        spi_transfer_t g_masterXfer;
        uint8_t * pRxBuf;
        status_t spiStatus;
        uint8_t g_dummyBuffer[260];

        memset(&g_masterXfer, 0, sizeof(spi_transfer_t));

        if(pRxBuffer == NULL)
        {
            pRxBuf = g_dummyBuffer;
        }
        else
        {
            pRxBuf = pRxBuffer;
        }

        /* Set up the transfer */
        g_masterXfer.txData = pTxBuffer;
        g_masterXfer.rxData = pRxBuf;
        g_masterXfer.dataSize = wTxLength;

        /* Start transfer */
        spiStatus =  SPI_MasterTransferBlocking(LPC_SPI_NFC,&g_masterXfer);

        if (spiStatus != kStatus_Success)
        {
            return (PH_DRIVER_FAILURE | PH_COMP_DRIVER);
        }

        if (pRxLength != NULL)
        {
            *pRxLength = wTxLength;
        }

        return PH_DRIVER_SUCCESS;
}

phStatus_t phbalReg_SetConfig(
                                         void * pDataParams,
                                         uint16_t wConfig,
                                         uint16_t wValue
                                         )
{
    return PH_DRIVER_SUCCESS;
}

phStatus_t phbalReg_GetConfig(
                                         void * pDataParams,
                                         uint16_t wConfig,
                                         uint16_t * pValue
                                         )
{
    return PH_DRIVER_SUCCESS;
}

Knowing that the SPI communication with the CLRC663 is in full duplex, do you have any idea where the error could come from?

Answer 1

I found out what my problem was. Here is how my reset was implemented:

HIGH - wait 20ms - LOW - wait 20ms - HIGH

In this document it is mentioned: "A hard power-down is enabled with HIGH level on pin PDOWN. ... To leave the power-down mode the level at the pin PDOWN as to be set to LOW."

However, I had to do the opposite and since I kept the reset pin at HIGH, the CLRC663 could not start, so it did not respond.