Simple Makefile not taking include path

Question

following is my makefile. but It is not taking include path during build.

SHELL   = /bin/sh
CC      = g++ 
FLAGS   = 
CFLAGS  = -fPIC 
TARGET  = my_bridge.so
INC=-I/my_custom_path/include/ -I/my_custom_path/include/linux

SOURCES = $(shell echo *.cpp)
HEADERS = $(shell echo *.h)
OBJECTS = $(SOURCES:.cpp=.o)

all: $(TARGET)

$(TARGET): $(OBJECTS)
    $(CC) $(FLAGS) $(INC) $(CFLAGS) -o $(TARGET) $(OBJECTS)

When I build i get following line

g++    -c -o my_bridge.o my_bridge.cpp

Answer 1

Your $(TARGET): $(OBJECTS) rule tells make how to generate my_bridge.so out of my_bridge.o, but you haven't given a rule that explains how to make my_bridge.o in the first place. make relies thus on its implicit rules for that, which gives you the command that you see. You can either define your own rule to compile .cpp files, e.g.

%.o: %.cpp
        $(CC) $(FLAGS) $(INC) $(CFLAGS) -o $@ $<

or put your include directive in $(CXXFLAGS), which is used by make's default rule (see https://www.gnu.org/software/make/manual/html_node/Catalogue-of-Rules.html#Catalogue-of-Rules)