I am having trouble with the basics of makefile.
I use gcc to compile
What I need to do is make a makefile named labMakefile and the targets are
lab
labM.o
labG.o
clean
the files already in the folder that i'm working on consist of
labM.c
labM.o
labG.c
labG.o
I have been looking at makefile tutorials but I cant seem to find the proper way to create a makefile
What i have tried
labMakefile: labM.o labG.o
but it just says labMakefile:: command not found
A makefile is a script which is run by Make. It is just a text file written with a strict grammar which Make needs, like source code (although it is interpreted, not compiled). You can use any text editor you like to create it.
You are using C (judging by the suffixes on your filenames). So to create labM.o from labM.c you'd probably use a command like
gcc -c labM.c -o labM.o
(Not that the -o labM.o is really needed, it's the default behavior, I'm just trying to spell things out a little.) Likewise to build labG.o you'd use
gcc -c labG.c -o labG.o
and then (I guess) you'd link them together to build lab:
gcc labM.o labG.o -o lab
And sometimes you'd want to clear out the constructed files:
rm -f *.o lab
So to do all of this, you'd write a makefile called Makefilethat looked like this (note that the leading spaces are TABs):
labM.o:
gcc -c labM.c -o labM.o
labG.o:
gcc -c labG.c -o labG.o
lab:
gcc labM.o labG.o -o lab
.PHONY:clean
clean:
rm -f *.o lab
Then you could make lab or make clean or make labM.o labG.o. If you really want to call this makefile labMakefile, you can do so, but then you'll have to do e.g. make -f labMakefile lab. This makefile is crude but effective. It could be greatly improved upon:
CC = gcc
lab: labM.o labG.o
gcc $^ -o $@
lab%.o: lab%.c
$(CC) -c $< -o $@
.PHONY:clean
clean:
@echo cleaning things up, boss...
@rm -f *.o lab
This will handle dependencies better: if you modify labM.c but not labG.c, and then make, Make will know that labM.o (and lab) must be rebuilt, but labG.o need not be.
This is a lot to take in, and further improvement is possible (dependency handling can be made very slick), but it's a good start.
To run a makefile, you must invoke "make"
If your makefile has not a standard name (makefile or Makefile), you should specify it with the -f argument :
make -f labMakefile
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