is it possible to use directory names in GNU make patterns?

Question

I have a number of device drivers: the source code for each device is in a sub-directory with the same name as the device:

devices/foo/foo.c
devices/bar/bar.c

If I set up an individual GNU make rule for each device like this, it works:

obj/foo.o: devices/foo/foo.c
    $(CC) $(CFLAGS) devices/foo/foo.c -o obj/foo.o

If I set up a make pattern like this, it is unable to work out how to make the file. I guess that the problem is to do with using a % as the name of the sub-directory.

obj/%.o: devices/%/%.c
    $(CC) $(CFLAGS) $< -o $@ 

Is there some way that I can set up a pattern to do this?

Answer 1

Another approach would be to define the following function expand in your makefile:

expand = devices/$1/$1.c

Then, having secondary expansion enabled, you can call that function for determining the prerequisites of the target based on the stem, which is in $*:

.SECONDEXPANSION:
obj/%.o: $$(call expand,$$*)
    $(CC) $(CFLAGS) $< -o $@