Is cache miss a kind of interrupt/fault

Question

We know that a page miss in memory will bring a page fault, and the page handler must load the page into the physical memory. Here I wonder whether a miss in a cache is also a system fault? If not, what's the difference between a memory fault and a cache fault? Thanks a lot.

Answer 1

By "cache fault" do you mean a cache miss in the L1/L2/L3 caches of the processor? If so, then no, it does not generate a fault, at least on every processor architecture that I've ever heard of.

The reason for this is that a page fault requires software intervention to decide whether the access was invalid, whether the access was to a page that was swapped out to disk, etc. In contrast, a cache miss can by definition be handled by the processor itself - since it didn't cause a page fault, the data must already be stored in main memory or a lower-level cache, which is directly accessible to the processor. The processor will mechanically translate the address of the memory being accessed from virtual to physical and then asks the lower-level cache or main memory for the data.

The same idea applies to simultaneous multiprocessors, where a cache line might be invalidated by one core which writes to it, even though another core has it stored in a cache. The processor defines its own coherency protocol to ensure that the stale copy will not be read, usually either by forcing the core with the invalid cache line to refresh it from a lower-level cache, or by requiring it to watch a shared write bus where all processors can see values which are being written to.