What would be the best way to initialize a Bundle Register to all 1s in Chisel?

Question

I'm wondering how can I initialize a Bundle register to all 1s. Let's say I have the bundle:

class MyBundle(val w: Int) extends Bundle {
  val a = UInt(w.W)
  val b = UInt(w.W)
  val x = Bool()
  val y = Bool()
}

I'm trying something like:

val myReg = RegInit(-1.S.asTypeOf(new MyBundle(32)))

However, this assumes width of the signed literal to be just 1, and initializes only the LSB of the bundle to 1. What comes to mind is:

val myReg = RegInit(-1.S(new MyBundle(32).asSInt().getWidth).asTypeOf(new MyBundle(32)))

But this does not seem to work at all.

How can I accomplish this?

Answer 1

You could set the width explicitly based on the width of that Bundle. You're on the right track. Try:

val myReg = RegInit(-1.S(new MyBundle(32).getWidth.W).asTypeOf(new MyBundle(32)))

Also note that if you've already constructed MyBundle you can refer to that directly as opposed to constructing new objects, e.g.:

val foo = Wire(new MyBundle(32))
val myReg = RegInit(-1.S(foo.getWidth.W).asTypeOf(foo))