Vhdl code simulation

Question

I'm trying to simulate the following code :

entity schal is port ( SW  : in bit_vector(7 downto 0);
       LED : out bit_vector(7 downto 0)); 
end schal;


architecture BEHAVIOUR of schal is 
begin 

INOUT_PROS : process (SW)
begin 
    LED <= SW; 

end process INOUT_PROS;
end BEHAVIOUR;

I wrote this do file

vsim work.schal
restart
view wave
radix hex
add wave -height 25 -radix default sim:/schal/*

force SW 01000001
run 20ns
force SW 01000000
run 20ns

here is what I get :

as you can see the simulation affect only the first bit but not the whole vector ? any idea how should I adjust the do file to get the right simulation ?

Answer 1

I think your force command is not using the correct syntax. You are trying to force a binary value, but the correct way to do this would be force SW 2#01000001, with the 2# specifying a binary value.

In ModelSim, go to Help > Documentation > PDF Bookcase, then open the 'Command Reference Manual'. This contains documentation on all commands, including force.