Verilog OR of array elements

Question

I want to OR a parameterized number of 32-bit buses as follows: out_bus = bus1 | bus2 | bus 3 | ... | bus N;

I also want to declare the buses as an array (N is a fixed parameter, defined at compile time):

reg [31:0] bus[N-1:0];

The best I can figure how to do this is something like this:

parameter N;
reg [N-1:0] temp;
reg [31:0] out_bus;
reg [31:0] bus[N-1:0];

always @(*) begin       
   for (j=0; j<32; j=j+1) begin : bits
     for (k=0; k < N; k=k+1) begin : bus
       temp = bus[k][j];
     end
     out_bus[j] = |temp;
   end
end

This need to be synthesizable. There's got to be a cleaner/better way, no?

Answer 1

If you were using SystemVerilog, you could replace the entire always block with

assign out_bus = bus.or();

Answer 2

This uses one fewer for loop and one fewer temporary signal:

reg [31:0] out_bus;
reg [31:0] bus[N-1:0];
integer k;

always @(*) begin       
    out_bus = {32{1'b0}};
    for (k=0; k < N; k=k+1) begin
        out_bus = out_bus | bus[k];
    end
end