Verilog - difference between %0d and %d [duplicate]

Question

I don't understand why some of the code example in the internet uses %0d to display the value of the variables and some of the code use %d? what are the difference between %0d and %d?

   data_1bit   = {32{4'b1111}};
   $display("data_1bit    = %0d",data_1bit);

   data_1bit_unsigned   = {32{4'b1111}};
   $display("data_1bit_unsigned  = %d",data_1bit_unsigned);

Answer 1

This is explained in section 21.2.1.3 Size of displayed data of the 1800-2012 LRM. %d displays using a fixed width to accommodate the largest possible value for the expression being displayed. %0d displays the minimum width, suppressing any leading 0's or spaces.

Answer 2

It simply removes unnecessary spaces introduced by the display statements. See example below-:

module xyz;

  integer a;

  initial
  begin
    a=8;
    $display("Value of a using percent__d = %d", a);
    $display("Value of a using percent_0d = %0d", a);
  end

endmodule

OUTPUT

Value of a using percent__d =           8
Value of a using percent_0d = 8