Turning on VHDL standard 2008 for Synopsys dc_shell analyzer

Question

I get trouble to get my code that is a correct VHDL (2008 release of language) code correctly analyzed by dc_shell. The case structure below that is valid 2008 generates an error

gen1: case myInt generate
   when 0 =>
       ...
   when 1 =>
       ...
   when 2 =>
       ...
  end generate;

I did not find in any part of the Synopsys design compiler documentation where it is described and if it supported or not.

Error:

106: gencfg: case nb_elem generate ^^^^

[Failure] Syntax error : received 'case'
          while expecting 'postponed'
                       or '(' or 'assert' or 'block' or 'component'
                       or 'configuration' or 'entity' or 'for' or 'if'
                       or 'process' or 'with' or IDENTIFIER or STRING LITERAL  
*** Presto compilation was unsuccessful. ***

VHDL Snippet is simple as that:

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity demo is

  generic (
    nbelem : positive range 1 to 6:= 6;
    regwid : positive := 14
    );

  port (
    data    : in  std_logic_vector(regwid-1 downto 0);
    app_clk : in  std_logic_vector(nbelem-1 downto 0);
    clk_out : out std_logic
    );

end demo;

architecture rtl of demo is

  constant selwid   : integer   := integer(ceil(log2(real(nbelem))));
  constant tied_up  : std_logic := '1';
  constant tied_low : std_logic := '0';

  signal sel : std_logic_vector(selwid-1 downto 0);

begin  -- architecture rtl

  -- selectors mapping
  -- NOTE: case style is vhdl08
  gen0: block
  begin
    gencfg: case nbelem generate
      when 5|6 =>
    sel <= data(15 downto 13);
      when 4|3 =>
    sel <= data(12 downto 11);
      when 2 =>
    sel <= data(9 downto 9);
      when 1 =>
    sel <= (others => tied_low);
    end generate gencfg;
  end block gen0;


  p0: process(all) is -- vhdl'08 syntax
    variable sel_v : integer;
  begin  -- process p0_b
    sel_v := to_integer(unsigned(sel));
    if (sel_v < nbelem and sel_v > 0) then
      clk_out <= app_clk(sel_v);
    else
      clk_out <= app_clk(0);
    end if;

  end process p0;



end architecture rtl;

Answer 1

The hdlin_vhdl_std variable controls how the Presto language frontend parses the VHDL code. It should be set to 2008 by default.

I had the same discussion with Synopsys. Although Presto claims to support VHDL2008, a lot of features are missing and I think will not be implemented in this "legacy" frontend.

Check your Synopsys documentation for "unified compile" which will enable you to use the VHDL 2008 features by using a different language frontend. However, this severley changes the flow and you might have to adapt your synthesis scripts etc. quite a bit.