The difference between dispatch,commit,issue and squash width in a cpu core

Question

Would someone explain me the difference between dispatch,commit,issue and squash width in a cpu core, which executes in an out of order fashion.

From what I know:

• issue width - how many instructions that can execute in parallel
• dispatch width - how many instructions that can be inside the reorder buffer(not sure)

and I have no idea of the other two. An explanation would be helpful

Answer 1

1. Issue Width: How many instructions can be pushed by decode into execute (EX) stage. Typically limited by size of issue queue (IQ) (in EX, instructions are first pushed into IQ and then "dispatched" to ALUs/Functional-Units for "real" execution)

2. Dispatch Width: How many instructions can move from IQ to ALUs/FUs. Limited by the number of ALUs/FUs, or how much of the IQ we read/cycle.

3. Commit/Squash Width: How many instructions are committed/squashed per cycle. GEM5 seems to be modelling bandwidth requirements that are associated with commit/squash per cycle (typically it involves removing entries from ROB and adjusting rename tables)