Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in intel

What is the proper OpenGL initialisation on Intel HD 3000?

c++ windows opengl intel

Ubuntu 13.10 can't satisfy dependency libpackagekit-glib2-14

linux ubuntu graphics intel drivers

L2 instruction fetch misses much higher than L1 instruction fetch misses

performance intel cpu-architecture cpu-cache perf

Java 8 Swing rendering problem with Intel HD 3700 linux

java swing user-interface intel freeze

Encouraging the CPU to perform out of order execution for a Meltdown test

linux-kernel x86 intel cpu-architecture exploit

Do FP and integer division compete for the same throughput resources on x86 CPUs?

performance assembly x86 intel cpu-architecture

Is there any situation where using MOVDQU and MOVUPD is better than MOVUPS?

assembly x86 x86-64 intel sse

Intel OpenCL SDK installation on ubuntu 14.04

sdk opencl intel ubuntu-14.04

What is the granularity of "masked" stores in AVX512?

performance assembly intel cpu-architecture avx512

How does loop address alignment affect the speed on Intel x86_64?

c++ optimization gcc intel x86-64

How to receive L1, L2 & L3 cache size using CPUID instruction in x86

caching x86 intel cpu-cache cpuid

Are RMW instructions considered harmful on modern x86?

assembly optimization x86 intel

Store forwarding Address vs Data: What the difference between STD and STA in the Intel Optimization guide?

performance assembly optimization intel cpu-architecture

Does `xchg` encompass `mfence` assuming no non-temporal instructions?

multithreading assembly x86 intel memory-barriers

Why wasn't MASKMOVDQU extended to 256-bit and 512-bit stores?

caching x86 intel cpu-architecture

Why does using MFENCE with store instruction block prefetching in L1 cache?

performance x86 intel memory-barriers prefetch

Wrong result from decryption using AES New Instruction Set

c encryption aes intel aes-ni

32-byte aligned routine does not fit the uops cache

performance assembly x86 intel cpu-architecture
« Newer Entries Older Entries »