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New posts in intel
Why are the user-mode L1 store miss events only counted when there is a store initialization loop?
Nov 06, 2021
x86
intel
performancecounter
cpu-cache
intel-pmu
May I do development of iPhone using VMWare on XP? [duplicate]
Mar 24, 2022
iphone
macos
vmware
intel
How can I write an application which utilizes Intel IPT hardware?
Aug 31, 2022
security
cryptography
hardware
intel
two-factor-authentication
.net code slower on AMD Opteron CPU
Aug 27, 2021
c#
.net
windows-server-2008
intel
amd-processor
Intel SGX simulator for Linux
May 31, 2022
intel
sgx
How to translate "pushl 2000" from AT&T asm to Intel syntax on i386
Apr 21, 2022
assembly
x86
intel
att
i386
64 bit Assembly introduction
Oct 24, 2022
assembly
64-bit
intel
About Adaptive Mode for L1 Cache in Hyper-threading
Jun 27, 2018
performance
intel
cpu-architecture
cpu-cache
hyperthreading
How do Intel CPUs that use the ring bus topology decode and handle port I/O operations
Apr 12, 2021
io
x86
intel
hardware
cpu-architecture
What does 'REX' stand for in an x86-64 REX prefix?
Aug 22, 2022
assembly
x86
x86-64
intel
machine-code
Optimizing an incrementing ASCII decimal counter in video RAM on 7th gen Intel Core
Jun 29, 2022
assembly
optimization
x86
intel
bootloader
Does using an Intel register for its "intended purpose" increase efficiency?
Jun 30, 2014
assembly
intel
std::function<> and the Intel compiler version 11.1
Jun 21, 2022
c++
lambda
intel
What is the best way to perform branching using Intel SSE?
Jun 28, 2022
assembly
compiler-construction
intel
sse
how verify that operating system support avx2 instructions
Oct 23, 2022
c
vectorization
intel
instruction-set
avx2
Do atomic_store/load from <stdatomic.h> work for unaligned, cross-cache-line data on Intel?
Dec 07, 2021
c
multithreading
gcc
clang
intel
The inner workings of Spectre (v2)
Aug 20, 2022
x86
intel
cpu-architecture
branch-prediction
spectre
Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?
Jun 01, 2022
assembly
x86
intel
cpu-architecture
instruction-set
Intel 64 and IA-32 | Atomic operations including acquire / release semantic
Aug 03, 2022
assembly
locking
x86
intel
memory-fences
Is it possible to program Intel's Trusted Platform Module
Apr 30, 2019
cryptography
hardware
intel
tpm
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