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New posts in assembly
How to read Assembly Opcode Reference?
Sep 18, 2025
assembly
x86
machine-code
opcode
instruction-encoding
How to tell the GNU assembler to warn when using undefined labels?
Sep 16, 2025
assembly
x86
bootloader
gnu-assembler
osdev
Does the flag register need to be saved when an interrupt occurs, or a process scheduling happens?
Sep 16, 2025
linux
assembly
linux-kernel
x86
What is the difference between assembly language of x86 and x64 architecture?
Sep 17, 2025
assembly
x86
x86-64
Is it possible to make writeable variables in .text segment using DB directive in NASM?
Sep 17, 2025
windows
assembly
x86
nasm
How to perform right shift in Y86-64 (or other toy ISAs with ADD + AND but no native right shift)
Sep 18, 2025
assembly
bit-manipulation
bit-shift
y86
How to prepare stack pointer for bare metal Rust?
Sep 17, 2025
assembly
rust
x86
bootloader
stack-pointer
How are instruction sets standardized?
Sep 17, 2025
assembly
x86-64
instruction-set
How can I exploit Buffer Overflow on x86-64 Linux?
Sep 16, 2025
assembly
x86-64
buffer-overflow
exploit
shellcode
Why is SIMD slower than scalar counterpart
Sep 16, 2025
assembly
x86
sse
simd
Bitwise operations in subleq
Sep 17, 2025
assembly
bitwise-operators
cpu-architecture
Arithmetic shift to divide by ODD number - Microprogrammed Control
Sep 16, 2025
assembly
architecture
bit-manipulation
How to exchange between 2 bits in a 1-byte number
Sep 16, 2025
assembly
x86
bit-manipulation
micro-optimization
CVTTSD2SI - a truncating instruction - uses rounding with "inexact" results?
Sep 16, 2025
assembly
x86
sse
floating-point-conversion
How are control flow graphs built in cases where the jump destination is based on a dynamic environment value?
Sep 16, 2025
assembly
x86
reverse-engineering
control-flow-graph
Linux x64 Calling Convention - Why are the first 6 args at negative offsets from RBP?
Sep 15, 2025
linux
assembly
x86-64
calling-convention
ELF label address
Sep 16, 2025
linux
assembly
x86
elf
relocation
Memory address and offset
Sep 16, 2025
assembly
Why the %r0 of SPARC or MIPS, is always 0?
Sep 16, 2025
assembly
mips
cpu-architecture
cpu-registers
sparc
x86 Assembly Add operands with different sizes
Sep 16, 2025
assembly
x86
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