String Manipulation in Verilog

Question

I need to perform basic operations on strings like concatenation,replacement and comparison in my Verilog simulation. How could it be possible? Is there any built-in support?

Thanks in advance.

Answer 1

There is no string datatype in Verilog however verilog does support string literals and using them as byte vectors. This is the example from the spec:

module string_test;
reg [8*14:1] stringvar;
initial begin
  stringvar = "Hello world";
  $display ("%s is stored as %h", stringvar,stringvar);
  stringvar = {stringvar,"!!!"};
  $display ("%s is stored as %h", stringvar,stringvar);
  end
endmodule

Since strings use the reg datatype you can use the normal operators to manipulate them, keeping in mind each character uses 8 bits.

5.2.3.1 String operations

The common string operations copy, concatenate, and compare are supported by Verilog HDL operators. Copy is provided by simple assignment. Concatenation is provided by the concatenation operator. Comparison is provided by the equality operators. When manipulating string values in vector regs, the regs should be at least 8*n bits (where n is the number of ASCII characters) in order to preserve the 8-bit ASCII code.

You'll have to write some tasks or functions if you need operations like searching.