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I am working on RISC-V 32I instructions recently. I got a question about NOP instruction, which the specification says it is equal to ADDI x0, x0, 0.
However, x0 is not a general register which can be modified by the programmer. Thus, why x0 serves as a destination register here for the NOP instruction?
Can anyone please shed some lights on this point?
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From The RISC-V Instruction Set Manual Volume I: Unprivileged ISA: The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0 .
The NOP instruction does nothing. Execution continues with the next instruction. No registers or flags are affected by this instruction. NOP is typically used to generate a delay in execution or to reserve space in code memory.
NOPs. A NOP is an instruction that does nothing (has no side-effect). MIPS assembler often support a nop instruction but in MIPS this is equivalent to sll $zero $zero 0 . This instruction will take up all 5 stages of pipeline.
RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry implementations.
NOP is a pseudoinstruction that expands to ADDI x0, x0, 0. The x0 (or zero) is a read-only register dedicated to the value zero, i.e., it is hardwired to zero for every single bit. Whatever is written to this register is simply discarded since its value can't be modified.
From The RISC-V Instruction Set Manual Volume I: Unprivileged ISA:
The
NOPinstruction does not change any architecturally visible state, except for advancing thepcand incrementing any applicable performance counters.NOPis encoded asADDI x0, x0, 0.
Keeping in mind that RISC-V has no arithmetic flags (i.e., carry, overflow, zero, sign flags), any arithmetic operation whose destination register is x0 will do as a no operation instruction regardless of the source registers since the net result will consist of advancing the program counter to the next instruction without changing any other relevant processor's state.
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