make file preprocessor directive

Question

I am not very experienced with make files and am trying to define a preprocessor variable in my make file,in Eclipse (linux).

It turns up a non trivial task,since as it seems am missing something...

Bellow you can find my make file's structure:

 var_first=g++

all:

    g++ main_cell.cpp -o hello

in this way am building my code,that i want to do is to define a variable in my make files that would then be asserted with an #ifdef,#endif in my code.

I have gone through numerous combinations but am missing some steps as it seems...

Could you please give some pointers?

Answer 1

To add a definition while compiling, use the -D g++ option. Like this:

g++ -DMyDefine=123 main_cell.cpp -o hello

Now in main_cell.cpp you can do:

#if MyDefine == 123
   doStuff();
#endif

To use makefile variables for this, do something like:

all: g++ main_cell.cpp -o hello -Dvar_first=$(var_first)

That is equivalent of #define var_first g++ in the .cpp file

Answer 2

If you want to pass the preprocessor variable directly to the compiler, you use a -D flag.

E.g. you want to define the variable PRE_MY_VAR to 1, you can write:

g++ -o myexecutable *.cpp -DPRE_MY_VAR=1

So in your makefile this would be:

all:
    g++ main_cell.cpp -o hello -Dvar_first="g++"