how to override/extend chisel signal naming

Question

It seems not an easy thing to do or even impossible, but we are using a naming convention that prefix or postfix signals with "i_" or "o_" for inputs/outputs in verilog.

Is there some method to mess with or override inside the chisel library to to that?

I saw that except for clock and reset, all signals have "io" prefix. Is is possible to use just "i" for input and "o" for output?

Answer 1

The easiest way to do this is to probably use a MultiIOModule. However, you can also do it with suggestName. Both approaches are shown below.

MultiIOModule

This a more flexible Module that lets you call the IO method to add ports to a module more than once. (Module requires that you define an io member and only allows you to call IO once.)

Because MultiIOModule frees you from the constraints of val io = ... you can use the prefix/postfix naming that you want with the names of your vals. Reflective naming will then get these right in the generated Verilog.

Consider the following Chisel code:

import chisel3._
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}

class Foo extends MultiIOModule {

  val i_bar = IO(Input(Bool()))
  val o_baz = IO(Output(Bool()))

  o_baz := ~i_bar

}

(new ChiselStage).execute(Array.empty, Seq(ChiselGeneratorAnnotation(() => new Foo)))

This produces the following Verilog:

module Foo(
  input   clock,
  input   reset,
  input   i_bar,
  output  o_baz
);
  assign o_baz = ~ i_bar;
endmodule

SuggestName

As an alternative, you can use the suggestName method to change the name to be different from what reflective naming (getting the name from the name of the val) would use.

Using suggestName you can coerce the names to be whatever you want. The following Chisel produces the same Verilog as above:

class Foo extends MultiIOModule {

  val a = IO(Input(Bool())).suggestName("i_bar")
  val b = IO(Output(Bool())).suggestName("o_baz")

  b := ~a

}