I have:
integer test[7:0];
but I cannot do:
test[0] = 0;
or
assign test[0] = 0;
or
intial
begin
test[0]=0;
end
or
integer test[7:0] = {0,0,0,0,0,0,0,0,0};
Any ideas? Just using 0 as an example, I need it to be 26, 40, 32, 18, 50, 0, 20, 12
Are you sure initial doesn't work (you might have a typo in there...)?
initial begin
for(int i=0; i<8; i++) begin
test[i] = i;
end
$display(test[4]);
end
In systemverilog, something like the following will work. These are known as "Assignment Patterns":
integer test[7:0] = '{26, 40, 32, 18, 50, 0, 20, 12}; // note the '
I doubt either of the above are synthesisable, except maybe when targeting an FPGA.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With