How does CPU access BIOS instructions stored in external memory?

Question

During the process of booting, CPU reads address of system BIOS from the Reset Vector and jumps to the location where BIOS is stored. My question here is:

*As BIOS is stored on some external memory like EEPROM (and not on main memory) , how does CPU access this external memory ?

*Is this external memory already mapped to some region of main memory? and does the CPU just jump to this mapped region to access BIOS instructions Or it actually accesses the instructions from external memory where BIOS is stored?

Answer 1

First I can refer you to a detailed article:

https://resources.infosecinstitute.com/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/#gref

But I will summarize here:

1. When CPU is "resetted", the reset vector interrupt (a specific memory address - 0xFFFFFFF0H) is executed - and the ROM content has to be there at that specific address.

Intel Reset Vector

How is the BIOS ROM mapped into address space on PC?

Who loads the BIOS and the memory map during boot-up

0xffff0 and the BIOS (hardwired address mapping is also explained/emphasized here)

2. When BIOS is executed, it will also initialize hardware like VGA, and initialize DRAM memory. Sometimes RAM memory and BIOS may overlapped, and usually the OS will takeover and reimplement all the functionalities of the BIOS (whis is specific to each motherboard).

What information does BIOS load into RAM?

https://resources.infosecinstitute.com/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/

Diagram below illustrate how motherboard designer will design the address ranges usable by the different hardware peripherals to lie in certain ranges, and the OS then has the responsibilities to allocate RAM ranges to lie in the unused by hardware regions. Don't forget that each core (for 32-bit) can only access 4GB memory - but phyical memory available can be much more than that. This is where pagetable comes in.

3. Once the pagetable is setup, then only the TLB and pagetable can be used - which is to provide indirect and efficient access to the RAM memory.