How does a 6502 CPU have an 8-bit data bus?

Question

How does the 6502 only have an 8-bit data bus if it needs 8 bits for the opcode, and 8 or 16 bits for data like an address or a number. Why wouldn’t it be 24-bits?

This is very confusing to me because I know the address bus can’t be used as data because it is Omni directional.

Answer 1

As per Synertek 8-Bit Microprocessor Family, SY6500, Apr 1979 (appendix A, unclear if part of the original doc)

This section contains an outline of the data on both the address bus and the data bus for each cycle of the various processor instructions. (...) All instructions begin with T0 and the fetch of the opcode and continue through the required number of cycles (...)

The document contains a concrete explanation for single byte instructions (ASL, DEX, NOP...):

The single byte instructions require two cycles to execute. During the second cycle the address of the next instruction will be placed on the address bus. However, the OP CODE which appears on the data bus during the second cycle will be ignored

Conversely, the data on the data bus on the 2nd cycle will be retained for 2 or 3 bytes instructions.

If we read "A.2.3. Absolute Addressing (4 cycles)", the table shows multiples fetches, one per cycle:

Tn	Addr bus	Data bus	Comments
T0	PC	OP CODE	Fetch OP CODE
T1	PC + 1	ADL	Fetch LSB EA
T2	PC + 2	ADH	Fetch MSB EA
T3	ADH,ADL	Data	Fetch Data

Note: the 6502 is part of the SY6500 family.

Answer 2

It's actually quite simple. The opcode is always one byte and it tells the CPU how many more bytes the CPU needs to read to get the complete instruction.

So, for example, take opcode $A9, looking at this table, we see it is LDA immediate. We see it is two bytes and we see it takes two machine cycles. In the first cycle, it loads the opcode. In the second cycle, it decodes the opcode and then increments the program counter, decides it needs to read another byte and loads that into the accumulator as well as incrementing the program counter.

Take a more complicated address e.g. LDA $01E0 This looks like AD E0 01 in memory (remember that the low byte of a 16-bit number comes first in memory, aka 'little-endian'). This takes three bytes but four cycles. This is because it loads the opcode in the first cycle, the low byte of the address in the second cycle, the high byte of the address in the third cycle and then it loads the value at that address in the fourth cycle.

I've simulated this in Visual6502 as follows:

I have put the instruction at address 0 and then stepped through until it was ready to fetch the next instruction which was a BRK.

Each cycle is broken into two halves. The reason for this being that the second half of every 6502 machine cycle is always a read from- or a write to memory without exception and much of the internal processing happens during the first half of the cycle.

So you can see:

• in cycle 0, the opcode AD is read
• in cycle 1, the low half of the address E0 is read
• in cycle 2, the high half of the address 01 is read
• in cycle 3, 01E0 is placed on the address bus and 55 is read from address location 01E0.

Answer 3

As per Synertek 8-Bit Microprocessor Family, SY6500, Apr 1979 (appendix A, unclear if part of the original doc)

This section contains an outline of the data on both the address bus and the data bus for each cycle of the various processor instructions. (...) All instructions begin with T0 and the fetch of the opcode and continue through the required number of cycles (...)

The document contains a concrete explanation for single byte instructions (ASL, DEX, NOP...):

The single byte instructions require two cycles to execute. During the second cycle the address of the next instruction will be placed on the address bus. However, the OP CODE which appears on the data bus during the second cycle will be ignored

Conversely, the data on the data bus on the 2nd cycle will be retained for 2 or 3 bytes instructions.

If we read "A.2.3. Absolute Addressing (4 cycles)", the table shows multiples fetches, one per cycle:

Tn	Addr bus	Data bus	Comments
T0	PC	OP CODE	Fetch OP CODE
T1	PC + 1	ADL	Fetch LSB EA
T2	PC + 2	ADH	Fetch MSB EA
T3	ADH,ADL	Data	Fetch Data

Note: the 6502 is part of the SY6500 family.