Connecting a module output to a register

Question

I have tried connecting a module output to a register, as follows:

module test
(
  input rst_n,
  input clk,
  output reg [7:0] count
);
  always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
      count <= 7'h0;
    end else begin
      if(count == 8) begin
        count <= count;
      end else begin
        count <= count + 1'b1;
      end
    end
  end
endmodule

module test_tb;
    reg clk;
    reg rst_n;
    reg [7:0] counter;

    initial begin
        clk = 1'b0;
        rst_n = 1'b0;
        # 10;
        rst_n = 1'b1;
    end
    always begin
        #20 clk <= ~clk;
    end

    test test1 (
        .rst_n(rst_n),
        .clk(clk),
        .count(counter) /* This is the problematic line! */
    );
endmodule

I got the error "Illegal output or inout port connection for "port 'count'" in ModelSim. Even though the error matches my code, I do not understand why, fundamentally, I cannot connect a module output to a register.

Why can I not connect a module output to a register in Verilog?

Answer 1

You can only assign a value to a reg within a procedural always block. You can not drive a reg from a module instance. That would be a continuous assisgnment.

Use a wire inside test_tb.