ARM: Why only 12 bits for immediate constants?

Question

what does it mean : I have only 12 bits for immediate constants, so can I represent immediate constants only from 0 to 2^12 = 4096 ? Operand 2 , if it's a register, can have 32 bits, but why only 12 bits for immediate constants? Where does this number come from?

Answer 1

It defined by the instruction set. E.g. the MOV instruction is encoded as

31 28 | 27 26 | 25 | 24 23 22 21 20 | 19   16 | 15    12 | 11        0      |
cond  | 0  0  | I  | 1  1  0  1  S  | SBZ     | Rd       | shifter operand  |

(see "ARM Architecture Reference Manual, 4.1.29 "MOV")

"Immediate" constants are encoded in the "shifter operand" which is 12 bits only. Other instructions have similar definitions are sometimes other widths.

This limitation exists because -- unlike on x86 -- instructions on ARM are always 32 bit or sometimes 16 bit when using Thumb(2). To support values which can not be expressed directly by a 12 bit binary digit, the shifter operand allows different addressing modes (e.g. left-shift, right-shift, rotating).