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This question is begging for a bunch of "why are you doing this?" responses.
I haven't been able to find this information in the 68k Programmer's Reference Manual, but that may be because I'm not sure of what verbiage to search for.
Here is the instruction format for the 68k's ADD opcode.
Bits 0-2 and 9-11 designate registers. What are the binary representations of the 68k's registers? Are they "addresses"?
Yes, I am aware that I can write a 68k assembly program and debug it to find this information. I'm looking for a reference. Thanks!
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Effective address (EA) is generated by adding a constant value to the content of an address register (the constant has 16 bits). e. g. ADD -$100(A4), D2; [[A4] - $100] + [D2] → D2. b) Full index mode.
The 68000 processor is characterized by a 16-bit external word length as the processor chip has 16 data pins for connection to the memory. However, data are manipulated inside the processor in registers that contain the 32 bits.
In this mode, the operand is in memory. The address of the operand is the sum of the address in the program counter (PC) and the sign-extended 16-bit displacement integer in the extension word. The value in the PC is the address of the extension word.
See Sec. 2.1, "Instruction Format":
An instruction specifies the function to be performed with an operation code and defines the location of every operand. Instructions specify an operand location by register specification, the instruction’s register field holds the register’s number; by effective address, the instruction’s effective address field contains addressing mode information; or by implicit reference, the definition of the instruction implies the use of specific registers. (emphasis added)
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